The basic SRAM cell can be formed using cross-coupled CMOS inverters having 2 each n-channel and p-channel transistors. The cell is accessed by, typically, 2 n-channel control gates for a standard SRAM cell and 4 control gates for 2-port memory devices. To conserve physical layout space, the p-channel transistors are often replaced with resistive loads.
Use of the p-channel transistors as the load devices for the SRAM cell, however, results in the cell having better electrical characteristics. Such cells are faster than those using resistive loads, since the p-channel transistors provide a higher drive current than high resistance devices. Also, use of p-channel transistors gives higher immunity to soft errors, such as those caused by alpha particle impacts and noise. The primary disadvantage of SRAM cells incorporating p-channel load transistors is that the layout area for each cell is significantly larger than those using resistive loads. This reduces device density and increases chip costs.
Bottom-gated polysilicon PMOS transistors, or an inverted form of the transistors, are often used as the p-channel transistors or load devices in the SRAM cell. Stacking the p-channel transistors over the n-channel transistors increases device density. Today, the polysilicon PMOS transistors are used, for example, as the load devices in four megabit SRAM cells to improve the stability of the cell and reduce the cell's stand-by current. These load devices, generally termed thin film transistors, may be built in 10 to 100 nanometers of polysilicon deposited on top of an oxide layer. In most applications, the gate of the thin film transistor is shielded at the bottom of the transistor body by a layer of oxide as shown in the prior art FIG. 1. After the gate 50 formation, a gate oxide layer is formed over the gate thus encapsulating the gate. A thin film of polysilicon 52 is deposited covering the gate. The thin film of polysilicon is appropriately doped to form an n-channel region above the gate and p* source and drain regions adjacent to the n-channel region and above the gate.
The typical bottom-gated thin film transistor, however, has a high grain-junction leakage current. The presence of grain boundary traps between, for example, the p.sup.+ drain region and the n-channel region causes field-enhanced generation current. This field enhanced current causes the leakage or off-state current of the cell to be high.
Several methods have been proposed to control the field-enhanced current in the bottom-gated polysilicon thin film transistor. See, for example, A. POLYSILICON TRANSISTOR TECHNOLOGY FOR LARGE CAPACITY SRAMs, by Ikeda et al, IEDM 469-472, 1990 and A 59 um.sup.2 SUPER LOW POWER SRAM CELL USING A NEW PHASE-SHIFT LITHOGRAPHY, by T. Yamanaka et al, IEDM 477-480, 1990. A gate to drain off-set structure of the polysilicon PMOS transistor is proposed whereby the leakage current and the stand-by dissipation power required for the memory cell are reduced to more acceptable levels.
As shown in prior art FIG. 2, the heavily doped p.sup.+ drain region 54 is offset from the transistor gate 50. However, the lightly doped n-channel region which extends further over the transistor gate has the same doping concentration as the gate which results in some additional current loss. It would therefore be desirable to provide an improved off-set structure which reduces the drain electric field without compromising the drive current. It would further be desirable to form the improved structure utilizing current fabrication techniques easily adapted for use with standard integrated circuit process flows.